FIG. 1 (PRIOR ART) is a cross-sectional simplified view of a portion of a double diffused metal oxide silicon (DMOS) transistor structure. An N- type epitaxial layer is disposed on an N+ type substrate 2. A P type body region 3 extends into the N- type epitaxial layer from the upper surface 4 of the N- type epitaxial layer to form an N-type epitaxial region 1. An N+ type source region 5 extends into the P type body region 3 from upper surface 4 so that a channel region 3A of the P type body region 3 exists between N+ source region 5 and the N- type epitaxial region 1 at upper surface 4. A gate 6 is disposed over the channel region 3A so that a layer of gate oxide 7 separates the gate 6 from the underlying N+ type source region 5, from the underlying P type channel region 3A, and from the underlying N- type epitaxial region 1. A source electrode S is shown connected to the source region, a gate electrode G is shown connected to the gate, and a drain electrode D is shown connected to the bottom surface of the substrate.
In operation, a positive voltage on gate 6 having a magnitude equal to or greater than a threshold voltage causes channel region 3A to invert, therefore allowing current to travel in a current path from drain electrode D, through N+ substrate 2, through N- type epitaxial region 1, through the inverted channel region 3A, through N+ type source region 5, and to source electrode S. Current flowing in this current path experiences a resistance R.sub.DS. As indicated in FIG. 1, resistance R.sub.DS to a first approximation is comprised of the resistance through the epitaxial region R.sub.EPI, the resistances R.sub.JFET and R.sub.ACC through the epitaxial silicon between adjacent P type body regions, and the resistance across the channel region
In many applications, including applications in which the DMOS power transistors are controlled by low voltage digital logic transistors, DMOS transistors having low threshold voltages are desired. Reducing the threshold voltage at which the channel region will invert may be accomplished in several ways including providing a body region 3 which is less heavily doped. If body region 3 is less heavily doped, a smaller positive voltage on gate 6 will be adequate to drive the smaller number of holes in channel region 3A out of the channel region and to invert the channel region.
It is, however, also a concern in DMOS transistors to reduce the source to drain resistance R.sub.DS. R.sub.DS may be decreased, for example, by increasing the N type dopant concentration of the epitaxial layer thereby making epitaxial region 1 more conductive and thereby reducing the R.sub.EPI, R.sub.JFET and R.sub.ACC components of R.sub.DS. FIG. 2 represents the dopant concentration of N and P type dopants at the upper surface 4 of the structure shown in FIG. 1. Because the P type body region 3 is formed into the N- type epitaxial layer, P type body region 3 has a background N type doping at the same concentration as epitaxial region 1. Similarly, because source region 5 is formed into P type body region 3, source region 5 is doped with P type dopants to the same concentration that channel region 3A is doped and is also doped with N type dopants to the same concentration as epitaxial region 1 is doped.
When the threshold voltage of the DMOS transistor is to be reduced by reducing the doping of the P type body region 3, the concentration of P type dopants in body region 3 has a concentration of a relatively low level such as the P type body concentration level 20 shown in FIG. 2. It is still desired, however, that the R.sub.DS of the DMOS transistor be as small as possible. The R.sub.DS of the device often cannot, however, be reduced as much as desired due to irregularities in the concentration of N type dopants in different regions of the epitaxial layer.
Body region 3 and source region 5 are typically formed by ion implantation. Implantation can be performed so that a fairly uniform dopant concentration is implanted. The growing of doped epitaxial silicon, in contrast, results in a concentration of dopants in the epitaxial silicon that may vary from region to region throughout the epitaxial layer. Epitaxial silicon grown in a batch reactor may have a dopant concentration that varies throughout a range of plus or minus approximately ten percent. Epitaxial silicon grown in a single wafer reactor may have a dopant concentration that varies throughout a range of plus or minus approximately five percent. These variations in dopant concentration may exist from transistor to transistor on the same wafer or may exist from wafer to wafer.
Accordingly, if the N type dopant concentration of the epitaxial region 1 (see level 21 in FIG. 2) is increased to where it is a significant proportion of the concentration of P type dopants of body region 3, local variations in epitaxial N- type dopant concentration will become a significant proportion of the total dopant concentration of the body region 3. As a result, irregularities in the doping concentration in the P body region 3 due to local epitaxial doping nonuniformities result in unpredictable depletion contours where the reverse biased PN junction between the P type body region 3 and the N- type epitaxial region 1 depletes inward toward the source region. A P type body region formed into a more heavily N doped portion of epitaxial region 1 will deplete inwards a farther distance toward the source region for a given PN junction reverse bias voltage than a similar P type body region disposed in a less highly N doped portion of epitaxial region 1. Because the body region is to withstand a given reverse bias without suffering punch-through, the P type doping of all the body regions throughout the wafer may have to be increased to prevent P body regions disposed in localized areas of more highly doped epitaxial silicon from punching through under the given reverse bias.
The variable doping concentration of various regions of the epitaxial layer may also result in the voltage threshold of one DMOS device on a wafer having a first threshold voltage whereas a second DMOS transistor formed in a different region of epitaxial silicon on the wafer or on another wafer has a second threshold voltage. Because the threshold voltages of the DMOS transistors must be fairly uniform for all DMOS transistors, conventional low threshold voltage DMOS devices typically employ relatively large areas of epitaxial silicon between adjacent P body regions in order to reduce R.sub.JFET, R.sub.ACC and R.sub.EPI by providing more silicon in the R.sub.DS current path. A large amount of silicon may therefore be consumed in conventional low threshold voltage DMOS structures to reduce R.sub.DS while maintaining a uniform low threshold voltage.